Mobility enhanced power CMOS

Author

Jaejune Jang ; Jaehyeon Jung ; Hoon Chang ; Yongdon Kim ; Seoin Park ; Hyunju Kim ; Jaehwan Kim ; Sangbae Yi

Author_Institution

Samsung Electron., Yongin, South Korea

fYear

2013

fDate

26-30 May 2013

Firstpage

155

Lastpage

158

Abstract

This paper introduces mobility enhanced 5V CMOS through geometry optimization in 130nm technology for state-of-the-art R_SP performance. By realizing <;100> channel direction on (100) wafer with grid-type layout, mobility of both NMOS and PMOS is enhanced in addition to increased effective width. Furthermore even higher mobility is achieved through introduction of biaxial compressive stress from nearby STI islands. As a result, I_DSAT and I_DLIN increase by 24%/29% for NMOS and 29%/37% for PMOS respectively compared to standard bar-type layout. All of this is obtained without any process change.

Keywords

CMOS integrated circuits; internal stresses; optimisation; power integrated circuits; power semiconductor devices; <;100> channel direction; (100) wafer; NMOS; PMOS; STI islands; biaxial compressive stress; geometry optimization; grid-type layout; mobility enhanced power CMOS; size 130 nm; voltage 5 V; CMOS integrated circuits; Compressive stress; Field effect transistors; Layout; Logic gates; MOS devices; Standards;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs (ISPSD), 2013 25th International Symposium on

Conference_Location

Kanazawa

ISSN

1943-653X

Print_ISBN

978-1-4673-5134-8

Type

conf

DOI

10.1109/ISPSD.2013.6694452

Filename

6694452