Passive inductors in silicon: A design proposal

Author

Nolasco, O. ; Sandoval, F. ; Ortega, E. ; Gurrola, J.

Author_Institution

Centro de Investig. y Estudios Av., CINVESTAV Unidad Guadalajara, Zapopan, Mexico

fYear

2013

fDate

13-15 Nov. 2013

Firstpage

1

Lastpage

6

Abstract

This paper present the induction phenomenon in planar inductors built with integrated circuit (IC) technology, and their analytical model description based on Greenhouse proposal, which not only incorporates the impact of no idealities of the substrate, but those parameters under the designer control, that are the support of every planar inductor design. To validate the design proposal, experimental results of a square inductor are presented, built with standard CMOS 5 volts, N Well, 0.5 micrometers process. The maximum relative error between the measured value, the simulated one, and the analytical one is more or less 4.5 percent.

Keywords

CMOS integrated circuits; elemental semiconductors; inductors; integrated circuit design; CMOS technology; Greenhouse proposal; induction phenomenon; integrated circuit technology; maximum relative error; model description; passive inductors; planar inductor design; silicon; Analytical models; Conductors; Inductance; Inductors; Integrated circuit modeling; Proposals; Substrates; CMOS technology; RF components; planar inductors; teaching;

fLanguage

English

Publisher

ieee

Conference_Titel

Power, Electronics and Computing (ROPEC), 2013 IEEE International Autumn Meeting on

Conference_Location

Mexico City

Type

conf

DOI

10.1109/ROPEC.2013.6702724

Filename

6702724