The SoC design for voice recognition with adaptive speedy discriminate algorithm

Smart and emerging technologies require fast processing hardware and software fusion solutions. In this paper we propose SoC design for voice recognition with adaptive speedy discriminate algorithm. In this order a tail of word is discriminated on conditional random fields. In this way the conditional random fields is calculated into speedy conditional random fields(SCRF). On this new fields voice detection algorithm become speedy. The detection algorithm is designed and implemented fully as hardware and the block architecture uses indexed register bank with 1 clock delay output and with minimum latency. The block fits in a Xilinx Vertex5 device requiring 45,110 LUTs. Additionally S3C6410 embedded board with processing ARM-11 was attached to device to further operations. The pointing input device SoC supports the proposed voice recognition will be fabricated.