• DocumentCode
    669700
  • Title

    Intrusive detection system implementation using deep packet inspection

  • Author

    Zoican, Sorin ; Zoican, Roxana

  • Author_Institution
    Telecommun. & Inf. Technol. Politeh. Univ. of Bucharest, Bucharest, Romania
  • Volume
    02
  • fYear
    2013
  • fDate
    16-19 Oct. 2013
  • Firstpage
    413
  • Lastpage
    416
  • Abstract
    One of the most common techniques to detect a network attack is to compare each incoming packet with pre-defined attack patterns. Scalability to network traffic and easy updating of new attack patterns are mandatory requirements needed to perform this comparison. The simplest way to implement such system is using the memory-based deterministic finite automata, but their storage requirement is growing exponentially with the number of patterns. Another issue is the computation time in order to detect the attack in real time. This work has the goal to propose an efficient deep packet inspection (DPI) algorithm and to analyze its efficiently implementation using a specialized hardware circuit and the GPU CUDA (Computer Unified Device Architecture) enabled boards existing in the personal computers. The following tasks have been analyzed: the parallelization of the pattern matching algorithm and the optimization of C code written for Nvidia compiler to obtain the best performance. A comparison of processing speed of implementation methods is illustrated.
  • Keywords
    C language; computer network security; deterministic automata; finite automata; graphics processing units; inspection; optimisation; packet radio networks; parallel architectures; parallel memories; pattern matching; telecommunication traffic; C code; CUDA; DPI algorithm; GPU; Nvidia compiler; computer unified device architecture; deep packet inspection; intrusive detection system implementation; memory-based deterministic finite automata; network attack detection; network traffic scalability; optimization; parallelization; pattern matching algorithm; personal computers; predefined attack pattern; specialized hardware circuit; storage requirement; Algorithm design and analysis; Graphics processing units; Hardware; Instruction sets; Kernel; Registers; CUDA technology; deep packet inspection; deterministic finite automaton; pattern search; significant symbol;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Telecommunication in Modern Satellite, Cable and Broadcasting Services (TELSIKS), 2013 11th International Conference on
  • Conference_Location
    Nis
  • Print_ISBN
    978-1-4799-0899-8
  • Type

    conf

  • DOI
    10.1109/TELSKS.2013.6704411
  • Filename
    6704411