High-speed NB-LDPC decoder for wireless applications

This paper presents a high-speed VLSI decoder for wireless applications, based on the generalized bit-flipping algorithm, suitable for decoding high-rate non-binary low-density parity-check codes. A technique to limit the data growth in the generalized bit-flipping decoding algorithm without penalizing the throughput is proposed. In addition, a broadcasting technique to reduce the routing congestion was applied to the derived message-passing architecture increasing the throughput of the decoder. Using a 90nm CMOS process, for the (837,723) non-binary code, the decoder requires an area of 13.4 mm², achieving 573 Mbps at 20 iterations.