Novel assembly framework of bi-layered molding materials for 3D-ICs packaging

As a high density arrangement of through silicon via (TSV) and thinner stacking chips are significantly required in the assembly technology of three-dimensional integrated circuits (3D-ICs) packages, finding a good approach during the processes of chip thinning to reduce the damage risk of stacked chips as well as to enhance the mechanical reliability of microbumps (μ-bump) has become the one of the important concerns for the development of 3D-IC packaging technology. To resolve the above-mentioned issue, this research proposes a promising approach that a chip to wafer (C2W) module with a combination of filling a proper underfill into the gaps between stacking chips and the use of an initialized molding material is considered. Compared with the traditional technical approach, the significant change in procedures is to fill into underfill during C2W fabricated process and consequently to implement chip thinning after the step of pre-stuffed molding material. The primary advantage of the foregoing implement is to decrease the mechanical load of thinning thickness exerted to stacking silicon chips by the support of neighboring molding material while a thickness of stacking chip highly scaled down to 30 μm and behind is attempted to be achieved. Another benefit by using this proposed approach is to have the potential of productivity because subsequent packaging process could be greatly simplified. Furthermore, a design of bi-layered molding is also taken into account to replace underfill and to reduce fabricated steps as well.