DocumentCode
671421
Title
Multilevel adaptive neural network architecture for implementing single-chip intelligent agents on FPGAs
Author
Finker, Raul ; del Campo, Ines ; Echanobe, Javier ; Doctor, Faiyaz
Author_Institution
Dept. of Electr. & Electron., Univ. of the Basque Country, Leioa, Spain
fYear
2013
fDate
4-9 Aug. 2013
Firstpage
1
Lastpage
9
Abstract
The powerful synergy of neural networks and reconfigurable hardware provides a solid foundation for the development of high performance embedded systems able to efficiently adapt to changing requirements. Adaptation at different levels - ranging from the physical level to the system level-can be combined to develop efficient solutions by means of FPGA technology. In this work, a multilevel adaptation scheme for the development of intelligent agents is proposed. Software learning algorithms are applied to adapt the agent behavior (i.e. neural network parameters) at the system level, while dynamic partial reconfiguration (DPR) is used to modify the agent at the physical and architectural level (i.e. neural network topology). Firstly, a multilevel adaptive intelligent agent is able to manage its resources efficiently in order to meet time-varying demands such as speed performance and power consumption. Secondly, from the behavioral viewpoint, multilevel adaptation provides the intelligent agent with high plasticity and flexibility. An FPGA-based intelligent agent has been successfully deployed for a real-time control problem in an inhabited intelligent environment. Results obtained show that the agent is able to adapt itself to changes in the environment in a lifelong mode.
Keywords
adaptive systems; embedded systems; field programmable gate arrays; learning (artificial intelligence); neural nets; FPGA technology; FPGA-based intelligent agent; dynamic partial reconfiguration; high performance embedded systems; multilevel adaptation scheme; multilevel adaptive intelligent agent; multilevel adaptive neural network architecture; neural network parameters; neural network topology; neural networks; real-time control problem; reconfigurable hardware; single-chip intelligent agents; software learning algorithms; Artificial neural networks; Hardware; Intelligent agents; Network topology; Neurons; Topology; Training;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks (IJCNN), The 2013 International Joint Conference on
Conference_Location
Dallas, TX
ISSN
2161-4393
Print_ISBN
978-1-4673-6128-6
Type
conf
DOI
10.1109/IJCNN.2013.6706760
Filename
6706760
Link To Document