Efficient and precise simulation model of synchronization clocks in packet networks

As packet technologies like Ethernet and IP are becoming the dominant in modern telecommunication networks, clock frequency and time synchronization over packet networks is an active area of research. Packet networks are asynchronous by design so frequency and time synchronization with sub-microsecond precision is a demanding task due to packet delay variations. A design of proper algorithms, that meet the telecommunication requirements, usually involves simulations over long period of time with nanoseconds resolution. Such precise and long-term simulation of synchronization performance is challenging, because of the vast amount of computer resources involved. This paper describes a simulation model that is both, efficient and highly precise. The model is able to simulate algorithms behavior over long period of time (tens of hours) while the computation time remains within interval of few minutes.