DocumentCode
675601
Title
0.42-to-1.20V read assist circuit for SRAMs in CMOS 65nm
Author
Abouzeid, Fady ; Clerc, Sylvain ; Pelloux-Prayer, B. ; Roche, Philippe
Author_Institution
STMicroelectron., Crolles, France
fYear
2013
fDate
7-10 Oct. 2013
Firstpage
1
Lastpage
2
Abstract
This work presents an ultra-low voltage SRAM read frequency boost circuit developed in 65nm to cover the lack of reliable sense amplifiers. This circuit enables full swing read speed-up and bitline leakage compensation from 1.2V to 0.42V. Embedded in a 65nm 32kb 10T SRAM, it offers 10% frequency gain and 10-to-90% leakage energy reduction from nominal to ultra-low voltage supply.
Keywords
CMOS integrated circuits; SRAM chips; low-power electronics; CMOS process; bitline leakage compensation; frequency gain; full swing read speed-up; leakage energy reduction; read assist circuit; read frequency boost circuit; size 65 nm; ultralow voltage SRAM; voltage 0.42 V to 1.20 V; Energy measurement; Frequency measurement; Integrated circuit modeling; Random access memory; SPICE; Silicon; Voltage measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013 IEEE
Conference_Location
Monterey, CA
Type
conf
DOI
10.1109/S3S.2013.6716578
Filename
6716578
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