Delay measurement of dual-rail asynchronous circuits for small-delay defect detection

As IC design has entered into the nanometer scale integration and multi-gigahertz systems, small-delay defects which are hard to be detected by traditional delay fault testing, might become a reliability issue as the defect might magnify during subsequent aging in the field. Asynchronous design is used to solve some of the problems that appear when using global clocks on very large circuits. Small-delay defects in dual-rail asynchronous circuits affect the performance and lifetime of chips. Thus, small-delay defects are desired to be detected in manufacturing testing. This paper proposes a delay measurement to detect small-delay defects in 4-phase dual-rail asynchronous circuits. The proposed method is based on a traditional on-chip delay measurement using delay value measurement circuit (DVMC). The proposed method measures path delay time by adding a DVMC and some MUXes. Experimental results show that, by using the proposed method, we can detect small-delay defects in 4-phase dual-rail asynchronous circuits with a small hardware overhead. Specifically, the hardware overhead are 0.25~6.22% for some benchmark circuits.