Read SNM free SRAM cell design in deep submicron technology

Data stability of Static Random Access Memory (SRAM) cell is a major issue in deep submicron CMOS technology. In this paper, a novel twelve transistor (12T) SRAM cell is proposed. The proposed cell demonstrates SNM free read operation and an enhanced static noise margin (SNM) for hold mode of the cell. The 12T SRAM cell is designed such that during the read operation, the switching threshold voltage (V_TRIP) of the inverter storing logic `1´ becomes high enough, which ensures that the cell does not flip even if a high amount of noise is injected on to the storage node storing logic `0´. The cell also provides better values for write margin. The simulations have been carried out on 45nm technology node with process parameter variations.