Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoC

High Level Synthesis (HLS) and design is gaining traction in commercial and academic circles, as an answer to increasing design complexity and short time-to-market. In this paper, we present a short survey on the HLS landscape and propose modeling concepts to extract and exploit the inherent flexibility for a commercially available high-level design tool, to explore ASIC and CGRA besides native ASIP support. Structural descriptions, representation, flexibility and limitations are discussed. Several case studies help highlight the advantages of the proposed methods, providing a solid framework to aid a broader and faster design space exploration.