Design of 65 nm CMOS SRAM for Space Applications: A Comparative Study

Author

Gorbunov, Maxim S. ; Dolotov, Pavel S. ; Antonov, A.A. ; Zebrev, Gennady I. ; Emeliyanov, Vladimir V. ; Boruzdina, Anna B. ; Petrov, Andrey G. ; Ulanova, Anastasia V.

Author_Institution

Sci. Res. Inst. of Syst. Anal., Moscow, Russia

Volume

61

Issue

4

fYear

2014

fDate

Aug. 2014

Firstpage

1575

Lastpage

1582

Abstract

We study the design of different 6T and DICE SRAM blocks based on a commercial 65 nm CMOS technology and discuss the experimental results for X-ray, proton and heavy ion irradiation campaigns. The results obtained show that the number of affected bits depends not only on LET value, but also on the location of a strike. MCU patterns are discussed. The sensitive area is estimated as the whole SRAM cell area after deduction of the region between N+ and P+ guard rings. The results for normally incident particles clearly showed the advantages and trade-offs of different circuit and layout techniques.

Keywords

CMOS memory circuits; SRAM chips; X-ray effects; integrated circuit layout; proton effects; radiation hardening (electronics); 6T SRAM block; CMOS SRAM; DICE SRAM block; LET value; MCU patterns; X-ray irradiation effect; dual interlocked cell; heavy ion irradiation effect; proton irradiation effect; size 65 nm; space application; strike location; Computer architecture; Layout; Microprocessors; Power supplies; Protons; Radiation effects; Random access memory; CMOS; DICE; MCU; RHBD; SBU; SEU; SRAM; TID; critical charge; guard rings; heavy ions; protons;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2014.2319154

Filename

6842704