• DocumentCode
    682957
  • Title

    Achievement of 15.1% total area efficiency on 1.09m2 monolithic CIGSeS modules in TSMC Solar production line

  • Author

    Sean Yang ; Kwang-Ming Lin ; Wen-Chin Lee ; Chih-Ching Lin ; Liham Chu

  • Author_Institution
    TSMC Solar Ltd., Taichung, Taiwan
  • fYear
    2013
  • fDate
    16-21 June 2013
  • Firstpage
    1741
  • Lastpage
    1743
  • Abstract
    15.1% total area efficiency on a monolithic 1.09m2 CIGSeS modules sets a new record for commercial-size, monolithic thin-film modules. This achievement results from improvements in both module design and thin-film composition, including: absorber improvement, cell redesign, and dead area reduction. Absorber improvement mainly consists of Selenization and Sulfurization (SAS) process optimization, resulting in open-circuit voltage (Voc) increase. Cell redesign mitigates the interconnect loss and maximize its benefit for Fill Factor (FF), while the reduction of the dead area increases module current. Production of modules with efficiency exceeding 15% is repeatable in the TSMC Solar production line located in Taichung, Taiwan.
  • Keywords
    solar cells; absorber improvement; cell redesign; dead area reduction; fill factor; interconnect loss; monolithic thin film modules; open circuit voltage; selenization and sulfurization process optimization; Manufacturing; Materials; Photonic band gap; Photovoltaic cells; Plasma measurements; Production; Synthetic aperture sonar;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Photovoltaic Specialists Conference (PVSC), 2013 IEEE 39th
  • Conference_Location
    Tampa, FL
  • Type

    conf

  • DOI
    10.1109/PVSC.2013.6744480
  • Filename
    6744480