Optimizing hardware cost of motion estimation module for H.264/AVC based on FPGA

H.264/AVC has excellent compression efficiency and network-friendly design, but it gets the advanced performance at the expense of highly complex calculation, resulting in huge hardware cost, especially motion estimation (ME) module. To reduce the logic resource consumption (LRC) without any obvious increase of the bit-rate, this paper simplifies the calculation of the block matching parameter with replaced pixel-bits and replaced pixels, and discusses how the LRC of ME module and the bit-rate are affected by the number of replaced bits and replaced pixels for different video motion scenes based on FPGA. The experimental results show three reasonable optimization approaches, in which the ratio of bit-rate increment is less than 0.47% and the LRC drops 24% to 45% compared with full search (FS) algorithm.