DocumentCode
686217
Title
Open critical area-constrained redundant via insertion
Author
Dan Xu ; Junping Wang ; Runsen Xing ; Jie Guo ; Zhanqi Xu
Author_Institution
Sch. of Telecommun. Eng., Xidian Univ., Xi´an, China
fYear
2013
fDate
25-27 Oct. 2013
Firstpage
1
Lastpage
4
Abstract
To improve via yield and reliability, redundant via insertion is a highly recommended technique proposed by foundries. However, inserting a redundant via can create extra open critical area between nets. A novel redundant via insertion method is proposed in this paper. In this work, we first address the problem of incremental open critical area for redundant via insertion, and then present an open critical area constrained redundant via insertion method. The experimental results show that under different extra open critical area constraint, the redundant via insertion rate declines in varying degrees. A large quantity of simulation data indicates that, when we choose 10% extra open critical area constraint, we can get a high insertion rate and have a good control of open critical area.
Keywords
integrated circuit reliability; integrated circuit yield; vias; open critical area constrained redundant via insertion; Integrated circuit modeling; Integrated circuit reliability; Layout; Manufacturing; Metals; Routing; Redundant via; integrated circuit; open critical area; yield;
fLanguage
English
Publisher
ieee
Conference_Titel
Anti-Counterfeiting, Security and Identification (ASID), 2013 IEEE International Conference on
Conference_Location
Shanghai
Type
conf
DOI
10.1109/ICASID.2013.6825305
Filename
6825305
Link To Document