A User-Configured Low Power Optimizing Mechanism on Embedded System

Currently, power management methods for embedded system are mainly implementations of DPM or DVS using workload-prediction techniques. A problem for this approach is that they are all purely hardware-oriented, regardless of factors such as software design and user´s demands, which actually drive the hardware to generate power consumption. In this paper, we propose a low power optimizing mechanism to reduce the power consumption of embedded systems using Task Decomposition on software and FSM (Finite-State Machine) on device driver. Also, we present a novel power management strategy called User-Configured Threshold Timeout/Sleep Strategy, in which power management strategy is dynamically adjusted in accordance with the actual needs of users. After simulations on S3C6410 embedded systems, we find that our proposed mechanism can reduce by up to 70.6% of the power consumption, with an average of 58.5%.