Design and analysis of bypassing multipler

Multiplication is one of the essential operations in Digital Signal Processing (DSP) applications like Fast Fourier Transform (FFT), Digital filters etc. Design of multiplier is done, considering the tradeoffs between low power and high speed. The Braun´s multiplier is one of the parallel array multiplier which is used for unsigned numbers multiplication. The dynamic power and delay of the Braun multiplier can be reduced by using the bypassing techniques i.e. 1-dimensional and 2-dimensional bypassing. This paper presents a comparative study of different bypassing multipliers on basis of area, power and delay for 4×4, 8×8 and 16×16 bits in FPGA Spartan - 3E using Xilinx 12.4 ISE tool and Synopsys.