Logic-in-memory based big-data computing by nonvolatile domain-wall nanowire devices

As one recently introduced non-volatile memory (NVM) device, domain-wall nanowire (or race-track) shows not only potential as future memory, but also computing capacity in big-data processing under unique domain-wall manipulation ability. In this paper, domain-wall nanowire device is studied for a NVM-based big-data computing platform, where all three parts: general purpose logic in LUT, special logic of XOR and data storage are all implemented by domain-wall nanowire devices. As one application, matrix multiplication, which is widely deployed in big-data applications such as machine learning or web searching, is studied in the proposed big-data computing platform. Experiment shows that when compared to CMOS based multi-core platform, the proposed computing platform exhibits 37x higher performance at the cost of 9x silicon area under the same power budget; and 4.2x better performance and 88.77% less power consumption under the same area constraint.