A comparison of high-frequency 32-bit dynamic adders with conventional silicon and novel carbon nanotube transistor technologies

The performances of high-frequency two-stage pipeline 32-bit carry lookahead adders are evaluated in this paper with the following three different implementations: silicon MOSFET (Si-MOSFET) domino logic, Si-MOSFET NP dynamic CMOS, and carbon nanotube MOSFET (CN-MOSFET) NP dynamic CMOS. While providing similar propagation delay, the total area of CN-MOSFET NP dynamic CMOS adder is reduced by 35.53% and 77.96% as compared to the conventional Si-MOSFET domino and Si-MOSFET NP dynamic CMOS adders, respectively. Miniaturization of the CN-MOSFET NP dynamic CMOS circuit reduces the dynamic switching power consumption by 80.54% and 95.57% as compared to the Si-MOSFET domino and Si-MOSFET NP dynamic CMOS circuits, respectively. Furthermore, the CN-MOSFET NP dynamic CMOS adder provides up to 99.98% savings in leakage power consumption as compared to the silicon circuits that are evaluated in this study.