Adaptive router with predictor using congestion degree for 3D Network-on-Chip

As the technology of chip multiprocessors (CMPs) is evolved, the performance of 2D architecture becomes insufficient to meet various requirements, and three-dimensional integrated circuits (3D-ICs) provide an attractive solution to improve network performance by using through silicon via (TSV). However, there are more transmitted packets in 3D network and congestion condition becomes more complex. The performance of network depends critically on its routing algorithm. Various routing algorithms have been proposed for 3D NoCs. Adaptive routing algorithm that merges local congestion and future congestion information was proposed in [9]. But the congestion used in it is roughly estimated, not very precise, but network performance is affected by the congestion significantly. In this paper, we propose a more precise congestion for predictor based on [9] and implement it in 3D NoCs. The proposed method is proved to have better latency and throughput than traditional routing methods like XY routing and Odd-even routing.