DocumentCode
693723
Title
Junctionless transistor: A review
Author
Amin, S. Intekhab ; Sarin, R.K.
Author_Institution
Dept. of ECE, Dr. B.R. Ambedkar Nat. Inst. of Technol. Jalandhar, Jalandhar, India
fYear
2013
fDate
18-19 Oct. 2013
Firstpage
432
Lastpage
439
Abstract
This paper is based on the extensive study of a Junctionless transistor. Since the entire conventional transistor have junction, which limits it´s scaling as it requires very abrupt junction, high concentration gradient and become challenging with every technology node. The problems comes when there is a junction in such a device like MOSFETs which has source junction and drain junction formed with oppositely doped substrate. A junctionless transistor is a uniformly doped nanowire without junction and no doping concentration gradient exist. It shows better short channel effect and less degradation in mobility with temperature, small DIBL, subthreshold swing and higher voltage gain which shows good scalability below 10nm and reduces the fabrication complexity. Junctionless transistor is a very promising candidate for future nano scale MOSFET device.
Keywords
nanowires; semiconductor device models; transistors; DIBL; doping concentration gradient; drain junction; junctionless transistor; nanoscale MOSFET device modelling; oppositely doped substrate; short channel effect; source junction; subthreshold swing; uniformly doped nanowire; Junctionless Transistor (JLT); MUGFET; SOI; Short channel effect;
fLanguage
English
Publisher
iet
Conference_Titel
Computational Intelligence and Information Technology, 2013. CIIT 2013. Third International Conference on
Conference_Location
Mumbai
Type
conf
DOI
10.1049/cp.2013.2625
Filename
6950909
Link To Document