Audio-video terminal system-on-chip simulation

In this paper, a system-on-chip design and simulation of an Audio-Video encoding terminal has been described. The purpose of this work was to model a multimedia mobile terminal in order to preliminarily explore system bottlenecks and inter-device communications. The system is based on two ST210[1] processors working in parallel, one dedicated to the compression of a video stream following the ITU-T H.263 [2] standard protocol, and the other one executing the ITU-T G.723 [3] speech compression. Data generated by the two processors are multiplexed together in an H.223-like [4] format. The ST210 cores are simulated using the VLIW-SIM [5][6] environment targeted for ST210 architecture. VLIW-SIM is a retargettable Instruction Set Simulator (ISS), pipeline and cycle accurate able to model state of the art VLIW (Very Long Instruction Word) architectures. The complete System has been simulated using the MaxSim SoC simulation environment[7][8]. Simulation test results for the complete system are reported.