Comparative study of different cache models on SimpleScalar architecture

This paper describes our work with the SimpleScalar simulator and the comparison of different cache models on the SimpleScalar architecture. The toolset can model simulations for a variety of platforms ranging from simple unpipelined processors to detailed dynamically scheduled microarchitectures with multiple-level memory hierarchies. However, inefficient caching increases the access time and reduces the overall efficiency of the toolset. To improve caching, Victim Cache has been added to Level-1 Cache, which significantly reduces the number of misses in it. Secondly, we added another level to the cache, extending it to Level-3 Cache. This will reduce the processing time as the processor has more cache storage to work with. This reduces the processing time by reducing the need for main-memory access, which is slower than cache access. Further, we have executed H.264/AVC codec, a video compression technique on our new architectures and compared the simulation results with the native SimpleScalar architecture.