Architectures for vector-tracing based motion estimation for MPEG2 type coding for TV and HDTV

A class of motion estimation VLSI architectures is presented which has been developed for the use in studio quality MPEG2 encoders. A new, fast motion estimation algorithm is applied which exploits both, temporal and spatial redundancies in motion vector fields and delivers near full search quality on large search windows. The proposed architectures are MIMD based, scalable both on chip and system level, and provide high flexibility according to a programmable RISC/´co-processor approach. A chip tailored to TV resolution requirements is under design. The same architecture principle can be used to build HDTV capable motion estimation devices.