DocumentCode
704689
Title
Analysis and implementation of ripple and area efficient charge pump circuits
Author
Bhatnagar, Vipul ; Pandey, Sujata ; Kumar, Pradeep
Author_Institution
Amity Sch. of Eng. & Technol., Amity Univ. Uttar Pradesh, Noida, India
fYear
2015
fDate
19-20 Feb. 2015
Firstpage
945
Lastpage
949
Abstract
In this paper the operation of different charge pump circuits are discussed and simulation is performed using 90nm CMOS technology to compare ripple, power dissipation and area. Since ripple in the output voltage depends on the size of capacitor used. The low value of ripple in the output comes at the cost of increased area. The simulated output is used to confirm reduced value of ripple. Output ripple with the size of the capacitors is used to determine and compare the quality of the charge pump circuits.
Keywords
CMOS integrated circuits; capacitors; charge pump circuits; CMOS technology; area cost; area efficient charge pump circuits; capacitor size; power dissipation; ripple efficient charge pump circuits; ripple value reduction; size 90 nm; Capacitance; Capacitors; Charge pumps; Layout; Logic gates; Simulation; Transistors; Charge pump for memories; area efficient charge pump techniques; ripple reduction;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing and Integrated Networks (SPIN), 2015 2nd International Conference on
Conference_Location
Noida
Print_ISBN
978-1-4799-5990-7
Type
conf
DOI
10.1109/SPIN.2015.7095373
Filename
7095373
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