An 8-bit programmable fine delay circuit with step size 65PS for an ultrawideband pulse position modulation testbed

This contribution discusses the design of a programmable delay shifter for an ultrawideband (UWB) pulse position modulation (PPM) testbed. PPM was selected because of its low duty cycle which translates to high power efficiency. The receiver synchronisation subsystem uses a digitally controlled delay shifter which is implemented in two parts: a coarse and a fine shifter. The resulting delay shift circuit is controlled by an 8-bit word and is designed to realise the delays with a granularity of 65.1 ps. The proposed combination of the delay step and fine delay components is a viable solution and the power consumption is comparable to a DDS solution.