Voltage scaling based low power high performance Vedic multiplier design on FPGA

Power is directly proportional to voltage. In this work, voltage scaling is applied in design of low power Vedic multiplier. There is 86-98% saving in leakage power and 4-9% saving in IOs power, when we scale down voltage from 1.5V to 0.5V. Vedic multiplier has now proven its supremacy on traditional multiplier in terms of performance, speed or delay. There is no research work is going on in energy efficient Vedic multiplier design. Dynamic voltage scaling technique is the mostly used power management technique. In order to fill this research gap, we are using voltage scaling in energy efficient Vedic multiplier design. We are taking 1.5V and 1.2V for overvolting and 1.0V and 0.5V for Undervolting. There are different IO standard available on Virtex-6 FPGA. In our project, we are taking these 12 different IO standards: HSTL_II, HSTL_II_18, HSTL_II_DCI (HIID), HSTL_II_DCI_18 (HIID18), HSTL_I, HSTL_I_12, HSTL_I_18, HSTL_I_DCI (HID), HSTL_I_DCI_18(HID18), LVCMOS12, LVCMOS18 and LVCMOS25.