Adopting multi-valued logic for reduced pin-count testing

The reduced pin-count test (RPCT) has been proposed for testing cost reduction in various scenarios like scan, test compression and multi-site test. In this paper, we propose a new RPCT technique in which several digital signals are combined into a single multi-valued logic (MVL) signal. Mixed-signal components, digital-to-analog and analogto- digital converters, are used to compress the tester channels and then to expand the test at the circuit under test. The method allows greater bandwidth efficiency than the existing SerDes alternative. However, the MVL signal can be sensitive to noise and nonlinearity errors. To ensure the reliability of test application, we provide an error control scheme. The paper gives theoretical analysis as well as experimental evidence.