NBTI-induced circuit aging optimization by protectability-aware gate replacement technique

Circuit aging induced by the negative bias temperature instability (NBTI) has become a major factor of reliability. The NBTI-induced aging of a logic gate can be mitigated by gate replacement technique only when the input gates of a logic gate are of some specific types. A protectability-aware gate replacement technique is proposed in this paper to mitigate NBTI-induced circuit aging. In the proposed technique the critical gates are identified by considering the impact of the types of input gates on their protectability, guaranteeing all the critical gates can be protected from static NBTI fatigue. Experimental results on ISCAS85 benchmark circuits under 45nm transistor model show that, compared with the techniques that neglect the impact of input gates´ type, the proposed scheme has up to more than 4, 7 and 10 times, on average, improvement on NBTI-induced delay degradation under timing margin 5%, 10% and 15%.