A 500-MHz high-speed, low-power ternary CAM design using selective match line sense amplifier in 65nm CMOS

The popularity of portable devices, multimedia devices and smart phones market leads to a rapid increase in the demand for high performance processors. Therefore a fast parallel processing memory that is capable of high speed parallel search operation, high storage capacity and power saving is inevitable. Ternary content addressable memory (TCAM) is a device which can help in the development of next generation high performance processors. It has high speed parallel processing memory where it can control the data at faster rates when the stored data and search data runs at the same period. High speed and power reduction are the two main criteria´s when designing a TCAM device for many applications. This paper focuses on these two criteria´s for TCAM design using a proposed match line sense amplifier (MLSA) for high performance processors like 3D vision processors. Simulations using 65nm 1.2V CMOS logic shows 34.21% of low power consumption and more than 40% of increase in search speed for TCAM one cell when compared to gate feedback (GF) and current race (CR) schemes.