On limit cycle oscillations in discrete-time digital linear regulators

Increasing level of transistor integration with multiple voltage domains and power states, ever decreasing decoupling capacitance, fast load transients and the need for fine-grained spatio-temporal power management provide impetus for embedding distributed point of load (PoL) linear regulators deep within digital functional blocks of microprocessors and Systems-on-Chip (SoCs). This demands modularity in design as well as process and voltage scalability of such linear regulators. Digital linear regulators have emerged as an attractive counterpart to the traditional analog solutions. This paper presents the circuit implementation and a steady state response model of a discrete-time digital regulator with simulations and hardware measurements with an emphasis on the steady state oscillations. We develop parametric models to demonstrate design trade-offs for a stable steady state response.