Positive-bias temperature instability (PBTI) of GaN MOSFETs

We have investigated the stability of the gate stack of GaN n-MOSFETs under positive gate stress. Devices with a gate dielectric that consists of pure SiO₂ or a composite SiO₂/Al₂O₃ bilayer were studied. Our research has targeted the evolution of threshold voltage (V_T), subthreshold swing (S) and transconductance (g_m) after positive gate voltage stress of different duration at different voltages and temperatures. We have also examined the recovery process after the stress is removed. We have observed positive V_T shift (ΔV_T) in both gate dielectrics under positive gate stress. In devices with a SiO₂ gate oxide, we have found that ΔV_T is caused by a combination of electron trapping in pre-existing oxide traps and interface trap generation. In devices with a composite SiO₂/Al₂O₃ gate oxide, on the other hand, ΔV_T is due to electron trapping in pre-existing oxide traps and generation of near interface oxide traps.