A novel erase method for scaled NAND flash memory device

Author

Chan-Ching Lin ; Kuei-Shu Chang-Liao ; Chen-Hao Huang ; Yi-Chung Liang ; Tzung-Bin Huang ; Hann-Ping Hwang

Author_Institution

Dept. of Eng. & Syst. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2015

fDate

27-29 April 2015

Firstpage

1

Lastpage

2

Abstract

In this paper, a novel erase method is proposed to modulate the electron tunneling region of 40 nm NAND flash memory device. The erasing electron can move to gate center from gate edge under back bias at 0.3V/-0.8V. The Fowler-Nordheim (FN) current of erase stress distributes on the whole channel region, not located at the gate edge region. Results show that the proposed method can improve cell reliability about 33%. TCAD analysis is employed to explain and prove the mechanism. This novel erase method is promising for scaled NAND flash memory.

Keywords

flash memories; integrated circuit reliability; logic gates; technology CAD (electronics); tunnelling; Fowler-Nordheim current; NAND flash memory device scaling; TCAD analysis; back bias; cell reliability improvement; electron tunneling region modulation; erase stress distribution method; erasing electron; gate center; gate edge region; size 40 nm; technology CAD (electronics); voltage -0.8 V; voltage 0.3 V; whole channel region; Electric fields; Electric potential; Flash memories; Logic gates; Performance evaluation; Process control; Reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Application (VLSI-TSA), 2015 International Symposium on

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/VLSI-TSA.2015.7117583

Filename

7117583