Predictive half-cell simulations of filament formation during IGBT turn-off

We present experimental data and simulation methods concerning the destruction of Insulated Gate Bipolar Transistors (IGBTs) during inductive turn-off when dynamic avalanche occurs. The influence of cell pitch and gate resistor on destruction is explored and the occurrence of current fllamentation is proposed to be a necessary condition for destruction. In order to validate this hypothesis, transient isothermal two-dimensional (2D) multi-cell simulations are performed. The simulation results reproduce the experimental results very well and reveal that the most critical conditions for fllamentation occur at that gate resistor value at which the discussed IGBT exhibits strongest avalanche generation. To replace the time demanding multi-cell simulations, an alternative simulation approach based on the occurrence of negative differential resistance in half-cell output characteristics is proposed and verified.