Automatic obfuscated cell layout for trusted split-foundry design

We present split-cellTK, a tool that automates the obfuscation of split-foundry layout, in which an untrusted foundry fabricates the devices (FEOL) and a trusted foundry completes the design with metalization (BEOL). split-cellTK does not alter the design netlist for obfuscation - it accepts an arbitrary transistor-level netlist as input. By obfuscating the the organization, placement and connectivity of devices in the FEOL, split-cellTK increases the difficulty of a reverse engineering effort. We evalute two FEOL obfuscation schemes: uniform layout and layout with random spacing. We extend the set of metrics previously defined in the literature to capture the benefits of obfuscation at the cell level. We use these metrics to evaluate the degree of obfuscation provided by our schemes and present the power, area, and throughput overheads for our obfuscation schemes. Finally, we present measured results for an asynchronous FPGA fabricated in a 65 nm split-foundry technology using our tool.