1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator for Improving Device Variation Tolerance

Author

Koike, Hiroki ; Miura, Sadahiko ; Honjo, Hiroaki ; Watanabe, Tosinari ; Sato, Hideo ; Sato, Soshi ; Nasuno, Takashi ; Noguchi, Yasuo ; Yasuhira, Mitsuo ; Tanigawa, Takaho ; Muraguchi, Masakazu ; Niwa, Masaaki ; Ito, Kenchi ; Ikeda, Shoji ; Ohno, Hideo ; E

Author_Institution

Center for Innovative Integrated Electron. Syst., Tohoku Univ., Sendai, Japan

fYear

2015

fDate

17-20 May 2015

Firstpage

1

Lastpage

4

Abstract

A device-variation-tolerant spin-transfer-torque magnetic random access memory (STT-MRAM) cell array design with a high-signal-margin reference generator circuit was developed to create high-density 1T1MTJ STT-MRAMs. To realize an appropriate STT-MRAM design, fluctuations in the memory cell characteristics were first measured using a 1-kbit STT-MRAM test chip. Based on these measurements, a reference generator and an STT-MRAM cell array architecture were proposed. This cell array was evaluated in terms of the signal margin for read operation and its tolerance to device variation by means of Monte-Carlo SPICE circuit simulations. The proposed design enables a 50% improvement in the signal margin compared with the conventional cell array circuit.

Keywords

MRAM devices; Monte Carlo methods; SPICE; logic design; logic testing; 1T1MTJ STT-MRAM cell array design; Monte-Carlo; SPICE; STT-MRAM test chip; adaptive reference voltage generator; circuit simulations; device-variation-tolerant spin-transfer-torque magnetic random access memory cell array design; high-signal-margin reference generator circuit; Arrays; Fluctuations; Generators; Microprocessors; Resistance; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2015 IEEE International

Conference_Location

Monterey, CA

Print_ISBN

978-1-4673-6931-2

Type

conf

DOI

10.1109/IMW.2015.7150264

Filename

7150264