A Highly Reliable and Cost Effective 16nm Planar NAND Cell Technology

Author

Kueber, William ; Puzzilli, Giuseppina ; Righetti, Niccolo ; Basco, Ricardo ; Lin Li ; Beltrami, Silvia ; Bertuccio, Massimo ; Camozzi, Elisa ; Daycock, David ; King, Matthew ; Larsen, Chris ; Karpan, Jeff ; Goda, Akira ; Roberts, Ceredig

Author_Institution

R&D Process Integration Dept., Micron Technol. Inc., Boise, ID, USA

fYear

2015

fDate

17-20 May 2015

Firstpage

1

Lastpage

4

Abstract

A 2D 16nm planar NAND cell technology is described with good cell to cell interference and reliability that can be used in a wide variety of applications. This second generation planar cell uses a high-K dielectric stack and a thin poly floating gate to maintain the needed gate coupling ratio and reduce adjacent cell interference. The technology includes select gates with the same planar structure as the cell. This select gate architecture simplifies the manufacturing of this NAND technology.

Keywords

NAND circuits; integrated circuit reliability; integrated memory circuits; 2D planar NAND cell technology; cell to cell interference; high-K dielectric stack; poly floating gate; reliability; size 16 nm; Computer architecture; Flash memories; Interference; Logic gates; Microprocessors; Nonvolatile memory; Reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2015 IEEE International

Conference_Location

Monterey, CA

Print_ISBN

978-1-4673-6931-2

Type

conf

DOI

10.1109/IMW.2015.7150269

Filename

7150269