• DocumentCode
    719526
  • Title

    A Study of Blocking and Tunnel Oxide Engineering on Double-Trapping (DT) BE-SONOS Performance

  • Author

    Lo, Roger ; Pei-Ying Du ; Tzu-Hsuan Hsu ; Chen-Jun Wu ; Jung-Yi Guo ; Chun-Min Cheng ; Hang-Ting Lue ; Yen-Hao Shih ; Tuo-Hung Hou ; Kuang-Yeu Hsieh ; Chih-Yuan Lu

  • Author_Institution
    Emerging Central Lab., Macronix Int. Co., Ltd., Hsinchu, Taiwan
  • fYear
    2015
  • fDate
    17-20 May 2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Double-trapping bandgap engineered SONOS (DT BE-SONOS) [1] was proposed to provide both fast erase speed and deep erase by means of a second nitride trapping layer and an additional blocking oxide on top of BE-SONOS. Although this provides excellent erase performance but the additional layers increase the EOT and subsequently the erase voltage, thus it is desirable to minimize their impact. This work investigates exhaustively the effect of thinning down the blocking layers. Since the ISPP and high temperature retention charge loss are mainly dominated by the ONO thickness of BE-SONOS below the blocking layers, reducing the blocking layer thickness has only minor impact on ISPP and retention. Moreover, erase saturation is determined by the dynamic balance of channel hole injection and gate electron injection. Experimental data show that reducing the thickness of the oxide between two trapping layers has little impact on erase saturation once the gate injected electrons are efficiently suppressed by the top most oxide. We have also investigated retention improvement by various oxides. By using HQ-SiO2 to replace the top tunnel ONO the trapped electron out-tunneling is reduced. Thus retention may be improved without increasing the effective oxide thickness.
  • Keywords
    integrated memory circuits; random-access storage; ISPP; SiO2; blocking oxide; channel hole injection; double-trapping bandgap engineered SONOS; gate electron injection; gate injected electrons; second nitride trapping layer; tunnel oxide engineering; Electric fields; Electron traps; Logic gates; SONOS devices; Transient analysis; Tunneling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Memory Workshop (IMW), 2015 IEEE International
  • Conference_Location
    Monterey, CA
  • Print_ISBN
    978-1-4673-6931-2
  • Type

    conf

  • DOI
    10.1109/IMW.2015.7150273
  • Filename
    7150273