Reliability verification of multi-power domain designs using an integrated approach of symbolic and geometry analysis

The paper describes verification techniques for certain layout design rules like deep n-well biasing, well implant and parasitic effects for mixed signal SOCs with multiple power domains. The technique analyzes the netlist and layout simultaneously and is superior to LVS methodology. Traditional LVS methodology is not effective because either some of these checks cannot be performed without putting in additional layout features or is not conducive to debugging. To explain our algorithm, we have shown examples of a Deep N-well biasing check and parasitic junction diode check because of multiple power domains. The verification technique and the algorithm presented in this paper were successfully used to verify 28nm and 20nm SOC designs with many power domains and internal derived supplies. All the errors reported were tagged with schematic and layout cross references along with the offending features, making it easier to identify and qualify the circuitry and signals for errors in question.