Experimental thermal characterization and thermal model validation of 3D packages using a programmable thermal test chip

In this paper, we present the experimental characterization of 3D packages using a dedicated stackable test chip. An advanced CMOS test chip with programmable power distribution has been designed, fabricated, stacked and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling, and soldered to the PCB. Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, thermal finite element and compact models are experimentally validated using a dedicated power map with multiple heat sources. Finally, the 3D test package is used to emulate the thermal behavior of a packaged memory-on-logic stack and to assess the thermal interaction between the chips.