3D heterogeneous integration structure based on 40 nm- and 0.18 µm-technology nodes

In this paper, a simple process for high yield CMOS-compatible and heterogeneous integrated chip-to-chip structure without TSV is demonstrated. This scheme provides two chips consisted of the shortest interconnect path by Cu/Sn pillar bump and electroless nickel immersion gold (ENIG) pad bonding. One of the key technologies of 3D integration process is bump plating on the uneven topography. Since passivation layer covers the periphery of the top metal layer, subsequent electroplating process resulted to the increase in height of bump edge which is higher than bump center resulting in concave shape. A new and unique plating solution was developed to solve the issue during the electroplating pillar bump. Basic electrical characteristics including resistance and current leakage were investigated with reliability tests. The stable reliability tests results and excellent electrical performance show that the 3D heterogeneous integration structure is potentially applicable for 3D applications in the future.