Modeling FinFET metal gate stack resistance for 14nm node and beyond

Author

Miyaguchi, Kenichi ; Parvais, Bertrand ; Ragnarsson, Lars-Ake ; Wambacq, Piet ; Raghavan, Praveen ; Mercha, Abdelkarim ; Mocuta, Anda ; Verkest, Diederik ; Thean, Aaron

Author_Institution

Imec, Leuven, Belgium

fYear

2015

fDate

1-3 June 2015

Firstpage

1

Lastpage

4

Abstract

A FinFET high-k replacement metal gate stack resistance model is proposed. Introduction of non-negligible contact resistance existing in boundaries between metal layers achieves a good model accuracy which is validated by FEM-based simulation results in 14nm and 10nm technology nodes. Impact of the contact resistance on digital and analog circuit is investigated, resulting in 20% degradation of analog speed by 5 Ω·μm² contact resistance. The derived gate resistance model is applicable to further downscaled FinFET technology.

Keywords

MOSFET; contact resistance; finite element analysis; semiconductor device models; FEM; FinFET metal gate stack resistance; contact resistance; finite element analysis; gate resistance model; high-k replacement metal gate stack resistance; size 14 nm; Contact resistance; FinFETs; Logic gates; Resistance; Tin; FinFET; Modeling; contact resistance; gate resistance; high-k replacement metal gate;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design & Technology (ICICDT), 2015 International Conference on

Conference_Location

Leuven

Type

conf

DOI

10.1109/ICICDT.2015.7165885

Filename

7165885