Triplet spike time dependent plasticity in a floating-gate synapse

Synapses plays an important role of learning in a neural network; the learning rules which modify the synaptic strength based on the timing difference between the pre- and post-synaptic spike occurrence is termed as Spike Time Dependent Plasticity (STDP). This paper describes the compact implementation of a synapse using single floating-gate (FG) transistor (and two additional high voltage transistors) that can store a weight in a non-volatile manner and demonstrate the triplet STDP (T-STDP) learning rule developed to explain biologically observed plasticity. We describe a mathematical procedure to obtain control voltages for the FG device for T-STDP and also show measurement results, from a FG synapse fabricated in TSMC 0.35μm CMOS process to support the theory.