DocumentCode
727157
Title
Design of a low power time to digital converter for flow metering applications
Author
Demarziani, Alberto ; Bonizzoni, Edoardo ; Maloberti, Franco ; D´Amato, Alessandro
Author_Institution
Dept. of Electr., Comput. & Biomed. Eng., Univ. of Pavia, Pavia, Italy
fYear
2015
fDate
24-27 May 2015
Firstpage
1646
Lastpage
1649
Abstract
This paper presents the design of an hybrid course-fine time to digital converter for low power applications. The core of the circuit consists of two current-mode SAR analog to digital converters working in a time-interleaved fashion. The TDC has been fully simulated at the transistor level with a 0.13-μm CMOS technology. The paper discusses the design details and the digital calibration techniques required to achieve a single-shot resolution of about 27 ps while keeping the power consumption below 600 μW.
Keywords
CMOS integrated circuits; calibration; flowmeters; time-digital conversion; CMOS technology; TDC; current-mode SAR analog to digital converter; digital calibration techniques; flow metering applications; low power time to digital converter; power 600 muW; size 0.13 mum; time interleave; transistor; Arrays; CMOS integrated circuits; Capacitors; Clocks; Power demand; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location
Lisbon
Type
conf
DOI
10.1109/ISCAS.2015.7168966
Filename
7168966
Link To Document