• DocumentCode
    735278
  • Title

    A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist

  • Author

    Kyung-Hoae Koo ; Liqiong Wei ; Keane, John ; Bhattacharya, Uddalak ; Karl, Eric A. ; Zhang, Kevin

  • Author_Institution
    Adv. Design, Logic Technol. Dev., Intel, Hillsboro, OR, USA
  • fYear
    2015
  • fDate
    17-19 June 2015
  • Abstract
    A 0.094μm2 8T SRAM bitcell is developed for a 14nm technology featuring FinFET transistors with a 70nm contacted gate pitch [1]. The bitcell and supporting circuitry are optimized for high density and aging tolerance. Supply collapse and wordline boosting techniques are applied for write VMIN assist. A delayed keeper is used for read VMIN improvement. A 400MHz VMIN of 560mV is achieved with the proposed design at -10°C in volume manufacturing.
  • Keywords
    MOSFET; SRAM chips; FinFET transistors; SRAM bitcell; aging tolerance; delayed keeper; high density; read and write assist; resilient 8T SRAM; size 70 nm; supply collapse; temperature -10 degC; voltage 560 mV; wordline boosting techniques; Aging; Arrays; Degradation; FinFETs; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSI Circuits), 2015 Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-4-86348-502-0
  • Type

    conf

  • DOI
    10.1109/VLSIC.2015.7231282
  • Filename
    7231282
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=735278