DocumentCode
735291
Title
0.65–0.73THz quintupler with an on-chip antenna in 65-nm CMOS
Author
Ahmad, Zeshan ; Kenneth, K.O.
Author_Institution
Dept. of EE, Univ. of Texas at Dallas, Richardson, TX, USA
fYear
2015
fDate
17-19 June 2015
Abstract
A passive frequency quintupler using a symmetric accumulation MOS varactor is demonstrated for the first time in CMOS. The broadband (0.65-0.73THz) quintupler with an on-chip antenna fabricated in a 65-nm bulk CMOS process reaches a setup limited peak Effective Isotropic Radiated Power (EIRP) of -22dBm at 726GHz, and a minimum conversion loss of 34dB. This highest order multiplier realized in CMOS has the highest EIRP among any lens-less silicon based signal generation circuit operating above 500GHz.
Keywords
CMOS integrated circuits; frequency multipliers; varactors; bulk CMOS process; effective isotropic radiated power; frequency 0.65 THz to 0.73 THz; frequency 726 GHz; loss 34 dB; on-chip antenna; passive frequency quintupler; signal generation circuit; size 65 nm; symmetric accumulation MOS varactor; Antennas; CMOS integrated circuits; Harmonic analysis; Impedance matching; Power generation; System-on-chip; Varactors;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-86348-502-0
Type
conf
DOI
10.1109/VLSIC.2015.7231303
Filename
7231303
Link To Document