A 10-b 1-GHz 33-mW CMOS ADC

Author

Sahoo, B.D. ; Razavi, Behzad

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA

Volume

48

Issue

6

fYear

2013

fDate

6/1/2013 12:00:00 AM

Firstpage

1442

Lastpage

1452

Abstract

This paper describes a pipelined analog-to-digital converter that resolves 4 b in its first stage and amplifies the residue by a factor of 2, thereby relaxing the opamp linearity, voltage swing, and gain requirements. Calibration in the digital domain removes the effect of capacitor mismatches and corrects for the gain error. Using a one-stage opamp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with a signal-to-(noise+distortion) ratio of 52.4 dB, achieving a figure of merit of 97 fJ/conversion-step.

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; capacitors; operational amplifiers; CMOS ADC; CMOS technology; calibration; capacitor mismatches; digital domain; frequency 1 GHz; gain error; gain requirements; one-stage opamp; opamp linearity; pipelined analog-to-digital converter; power 33 mW; size 65 nm; voltage swing; word length 10 bit; word length 4 bit; CMOS integrated circuits; Calibration; Capacitance; Capacitors; Equations; Gain; Noise; Analog-to-digital converter (ADC); gain error calibration; low power; low-gain opamp; multibit capacitor mismatch calibration; pipelined ADC;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2013.2252518

Filename

6493461