A Noise-Cancelling Receiver Resilient to Large Harmonic Blockers

By employing two passive-mixer-based downconversion paths, a recently proposed noise cancelling receiver achieves a low-noise figure and tolerates most out-of-band blockers up to 0 dBm with little performance degradation. However, like most wideband passive-mixer-based designs, the architecture is far less tolerant of harmonic blockers, that is blockers located at or around precise integer multiples of the LO frequency. These blockers are problematic because they are downconverted inside the bandwidth of the baseband TIAs and, so, experience significant on-chip voltage gain. This work presents an enhanced noise-cancelling architecture that prevents harmonic blockers experiencing large on-chip gain, thereby boosting the receiver´s resilience to such blockers. It will be shown that separate techniques are required for the voltage-driven main path and the current-driven auxiliary path. To validated these ideas, single-ended and fully-differential prototypes were fabricated in 28 nm silicon.