• DocumentCode
    73993
  • Title

    Tunable Peeling Technique and Mechanism of Thin Chip From Compliant Adhesive Tapes

  • Author

    Zunxu Liu ; YongAn Huang ; Jiankui Chen ; Zhouping Yin

  • Author_Institution
    State Key Lab. of Digital Manuf. Equip. & Technol., Huazhong Univ. of Sci. & Technol., Wuhan, China
  • Volume
    4
  • Issue
    4
  • fYear
    2014
  • fDate
    Apr-14
  • Firstpage
    560
  • Lastpage
    568
  • Abstract
    The efficient pick-up of thin/ultrathin integrated circuit chip from the wafer is one of the key techniques in advanced microelectronic packaging, whose success rates are determined by the peeling-off of chip from the adhesive tapes. Analytical models for estimating the effects on process parameters represent important design tools. Here, solutions for adhesive stresses and mixed-mode peeling are presented in chip-adhesive-substrate structure based on mixed boundary conditions, in which the geometrical dimensions and material properties of this three-layer system are included. Analytical expressions are defined in terms of structural parameters and several integration constants, which can be obtained by a given system of linear equations. These models agree well with finite element models with virtual crack-closure technique. In particular, the mechanism of tunable mode peeling is uncovered, and the technological limit of normal single ejecting needle is discussed.
  • Keywords
    adhesives; finite element analysis; integrated circuit modelling; integrated circuit packaging; adhesive stresses; analytical expressions; analytical models; chip-adhesive-substrate structure; compliant adhesive tapes; finite element models; integrated circuit chip; linear equations; material properties; microelectronic packaging; mixed boundary conditions; mixed-mode peeling; thin chip mechanism; three-layer system; tunable peeling technique; virtual crack-closure technique; wafer; Analytical models; Equations; Force; Mathematical model; Stress; Substrates; Adhesive stresses; energy release rate (ERR); microelectronic fabrication/packaging; pick-up process; tunable peeling;
  • fLanguage
    English
  • Journal_Title
    Components, Packaging and Manufacturing Technology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    2156-3950
  • Type

    jour

  • DOI
    10.1109/TCPMT.2014.2298036
  • Filename
    6720172